Authors

Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen

Abstract

In this paper, we propose a novel on-chip router architecture for avoiding congested areas in regular two-dimensional on-chip networks. This architecture takes advantage of an efficient adaptive routing model based on the Hamiltonian path for both the multicast and unicast traffic. The output selection of the proposed architecture is based on the congestion condition of neighboring routers and the input selection is based on the Weighted Round Robin mechanism which allows packets to be serviced from each input port according to its congestion level. The simulation results show that in multicast, unicast, and mixed traffic profiles the proposed model has lower average delays and lower average and peak power compared to previously proposed models.

Citation

  • Journal: 2010 IEEE Computer Society Annual Symposium on VLSI
  • Year: 2010
  • Volume:
  • Issue:
  • Pages: 92–97
  • Publisher: IEEE
  • DOI: 10.1109/isvlsi.2010.76

BibTeX

@inproceedings{Daneshtalab_2010,
  title={{Input-Output Selection Based Router for Networks-on-Chip}},
  DOI={10.1109/isvlsi.2010.76},
  booktitle={{2010 IEEE Computer Society Annual Symposium on VLSI}},
  publisher={IEEE},
  author={Daneshtalab, Masoud and Ebrahimi, Masoumeh and Liljeberg, Pasi and Plosila, Juha and Tenhunen, Hannu},
  year={2010},
  pages={92--97}
}

Download the bib file

References

  • Boppana, R. V., Chalasani, S. & Raghavendra, C. S. Resource deadlocks and performance of wormhole multicast routing algorithms. IEEE Trans. Parallel Distrib. Syst. 9, 535–549 (1998) – 10.1109/71.689441
  • Abad, P., Puente, V. & Gregorio, J.-A. MRR: Enabling fully adaptive multicast routing for CMP interconnection networks. 2009 IEEE 15th International Symposium on High Performance Computer Architecture 355–366 (2009) doi:10.1109/hpca.2009.4798273 – 10.1109/hpca.2009.4798273
  • Zeferino, C. A., Kreutz, M. E. & Susin, A. A. RASoC: a router soft-core for networks-on-chip. Proceedings Design, Automation and Test in Europe Conference and Exhibition 198–203 doi:10.1109/date.2004.1269230 – 10.1109/date.2004.1269230
  • Wu, D., Al-Hashimi, B. M. & Schmitz, M. T. Improving routing efficiency for network-on-chip through contention-aware input selection. Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC ’06 36 (2006) doi:10.1145/1118299.1118310 – 10.1145/1118299.1118310
  • Nilsson, E., Millberg, M., Oberg, J. & Jantsch, A. Load distribution with the proximity congestion awareness in a network on chip. 2003 Design, Automation and Test in Europe Conference and Exhibition 1126–1127 doi:10.1109/date.2003.1253765 – 10.1109/date.2003.1253765
  • Demers, A., Keshav, S. & Shenker, S. Analysis and simulation of a fair queueing algorithm. Symposium proceedings on Communications architectures & protocols 1–12 (1989) doi:10.1145/75246.75248 – 10.1145/75246.75248
  • Ye, T. T., Benini, L. & Micheli, G. D. Packetization and routing analysis of on-chip multiprocessor networks. Journal of Systems Architecture 50, 81–104 (2004) – 10.1016/j.sysarc.2003.07.005
  • Jian Liang, Swaminathan, S. & Tessier, R. ASOC: a scalable, single-chip communications architecture. Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622) 37–46 doi:10.1109/pact.2000.888329 – 10.1109/pact.2000.888329
  • Gupta, P. & McKeown, N. Designing and implementing a fast crossbar scheduler. IEEE Micro 19, 20–28 (1999) – 10.1109/40.748793
  • Orion: A Power-Performance Simulator for Interconnection Network. Proc Hot Interconnects (2002)
  • hu, DyAD-Smart Routing for Networks-on-Chip. DAC 2004 (2004)
  • Ge-Ming Chiu. The odd-even turn model for adaptive routing. IEEE Trans. Parallel Distrib. Syst. 11, 729–738 (2000) – 10.1109/71.877831
  • Glass, C. J. & Ni, L. M. The Turn Model for Adaptive Routing. [1992] Proceedings the 19th Annual International Symposium on Computer Architecture 278–287 doi:10.1109/isca.1992.753324 – 10.1109/isca.1992.753324
  • Ebrahimi, M., Daneshtalab, M., Liljeberg, P. & Tenhunen, H. HAMUM - A Novel Routing Protocol for Unicast and Multicast Traffic in MPSoCs. 2010 18th Euromicro Conference on Parallel, Distributed and Network-based Processing 525–532 (2010) doi:10.1109/pdp.2010.81 – 10.1109/pdp.2010.81
  • Daneshtalab, M., Ebrahimi, M., Mohammadi, S. & Afzali-Kusha, A. Low-distance path-based multicast routing algorithm for network-on-chips. IET Comput. Digit. Tech. 3, 430–442 (2009) – 10.1049/iet-cdt.2008.0086
  • Carara, E. A. & Moraes, F. G. Deadlock-Free Multicast Routing Algorithm for Wormhole-Switched Mesh Networks-on-Chip. 2008 IEEE Computer Society Annual Symposium on VLSI 341–346 (2008) doi:10.1109/isvlsi.2008.18 – 10.1109/isvlsi.2008.18
  • duato, Interconnection networks: an engineering approach. (2003)
  • Benini, L. & De Micheli, G. Networks on chips: a new SoC paradigm. Computer 35, 70–78 (2002) – 10.1109/2.976921
  • Glass, C. J. & Ni, L. M. The Turn Model for Adaptive Routing. [1992] Proceedings the 19th Annual International Symposium on Computer Architecture 278–287 doi:10.1109/isca.1992.753324 – 10.1109/isca.1992.753324